Quatech RS-232 Instrukcja Użytkownika Strona 1

MPAC-100RS-232 PCISYNCHRONOUS ADAPTERfor PCI Card Standard compatible machinesUser's ManualQUATECH, INC. TEL: (330) 434-3154662 Wolf Ledges Parkw

3. On the next dialog, select the "CD-ROM drive" checkbox. Insert the QuatechCOM CD (shipped with the card) into the CD-ROM drive. Click t

5. Windows will copy the INF file from the CD and display a final dialogindicating that the process is complete. Click the "Finish" button.

3.2 Viewing Resources with Device ManagerThe following instructions provide step-by-step instructions on viewingresources used by the MPAC-100 in Wind

5. Click the "Resources" tab located along the top of the properties box to view theresources Windows has allocated for the MPAC-100 match t

4 Other Operating SystemsDevice drivers for Windows NT and OS/2 are also available for the MPAC-100.The board can be used under DOS and other operatin

Quatech's "QTPCI" utility supplies the information required when modifyingthe serial port settings of the application. This program sh

The QTPCI program is capable only of displaying the PCI configuration. It cannotbe used to make changes.Q - Quatech PCI adaptersN - Other PCI devices

and I/O regions, etc. Pressing the "N" key will show similar information for allnon-Quatech PCI devices in the system, including those devi

5 Using the MPAC-100 with SyncdriveSyncdrive is a synchronous communications software driver package designedto aid users of Quatech synchronous commu

6 AddressingThe MPAC-100 occupies a continuous 16-byte block of I/O addresses. Forexample, if the base address is set to 300 hex, then the MPAC-100 w

WARRANTY INFORMATIONQuatech Inc. warrants the MPAC-100 to be free of defects for one (1) year fromthe date of purchase. Quatech Inc. will repair or r

7 InterruptsThe MPAC-100 will operate using the interrupt level (IRQ) assigned by the PCIsystem. Interrupts can come from the SCC, the internal FIFOs

8 SCC General InformationThe Serial Communications Controller (SCC) is a dual channel, multi-protocoldata communications peripheral. The MPAC-100 pro

8.1 Accessing the registersThe mode of communication desired is established and monitored through thebit values of the internal read and write registe

Example 3: Write data into the transmit buffer of channel A.mov dx, base ; load base addressout dx, al ; write data in ax to buffer Example 4: Read

for its clock-on-receive. Programming of the clocks should be done before enabling thereceiver, transmitter, BRG, or DPLL.External/Status interrupt c

8.2 Baud Rate Generator ProgrammingThe baud rate generator (hereafter referred to as the BRG) of the SCC consists ofa 16-bit down counter, two 8-bit t

8.4 Support for SCC Channel B The MPAC-100 is a single-channel device. Portions of SCC channel B are used toaugment channel A. Channel B cannot be

8.5 SCC Incompatibility Warnings Due to the SCC implementation used by the MPAC-100, there are two minorincompatibilities that the software programme

9 FIFO OperationThe MPAC-100 is equipped with 1024-byte internal FIFOs in the transmit andreceive data paths. These FIFOs are implemented as extensio

9.2.2 Receive FIFOThe receive FIFO can service the receiver of either channel A or channel B of theSCC. If RXSRC (bit 1) of the Configuration Registe

Copyright 2000 Quatech, Inc.NOTICEThe information contained in this document is protected by copyright, andcannot be reproduced in any form without th

9.3.1 Using channel A for both transmit and receiveThis is the mode in which most applications will run. Set RXSRC (bit 1) in theConfiguration Regis

9.3.2 Using channel B for receiveThe MPAC-100 supplies only limited support for SCC channel B. This mode,therefore, is not recommended for most appli

9.4 FIFO status and controlSeveral registers are used to control the FIFOs and monitor their status. Theseregisters are detailed in other chapters of

IMPORTANTSoftware can differentiate between the two types ofRX_FIFO interrupts by examining the RXH bit inthe FIFO Status Register. If RXH is clear (

9.6 Receive pattern detectionThe internal FIFOs are most useful in bit-synchronous operational modesbecause the SCC can generate a Special Condition i

9.7 Receive FIFO timeoutWith asynchronous operational modes, the same problem exists. Namely, howis one to determine when a reception is complete? W

10 Communications RegisterThe Communications Register is used to set options pertaining to the clocks.The source and type of clock to be transmitted o

SW_SYNC ('C' option is used)This bit is used to drive the active-low SYNC input of the channel Areceiver. The SYNC signal is asserted when

11 Configuration RegisterThe Configuration Register is used to set the interrupt source and enable theinterface between the SCC and the internal FIFOs

Bit 1: RXSRC --- Receive FIFO DMA Source: Thisbit determines which SCC pins are used to control transmit and receiveDMA transactions between the SCC a

4214 FIFO Control Register...4113 FIFO Status Register...4012 Interrup

12 Interrupt Status RegisterThe Interrupt Status Register is used to determine the cause of an interruptgenerated by the MPAC-100. The address of thi

13 FIFO Status RegisterThe FIFO Status Register is used to return current status information about theinternal FIFOs. The address of this read-only r

14 FIFO Control RegisterThe FIFO Control Register is used to control the internal data FIFOs. Theaddress of this register is Base+A (hex). Table 13

15 Receive Pattern Character RegisterThe Receive Pattern Character Register is used to set the character value to beused in receive pattern detection.

16 Receive Pattern Count RegisterThe Receive Pattern Count Register is used to set the counter value to be used inreceive pattern detection. The addr

17 Receive FIFO Timeout RegisterThe Receive FIFO Timeout Register is used to control the operation of theinternal receive FIFO timeout feature. The a

18 External ConnectionsThe MPAC-100 is configured as a Data Terminal Equipment (DTE) device,meeting the RS-232-D standard using a DB-25 male connector

N/CN/CRxCLK (DTE)SYNCAN/CCDDGNDDSRCTSRTSRxDTxDCGND13121110987654321252423222120191817161514TM (OUTPUT)TxCLK (DTE)N/CN/CRLBK (OUTPUT)DTRN/CLLBK (OUTPUT

If Card and Socket Services has set the SIGCHG bit in the PCI ConfigurationStatus Register to a logic 1, the RING signal is routed to the STSCHG line

18.4 Null-modem cablesThe MPAC-100 does not use a standard asynchronous PC serial port connectorpinout. Typical off-the-shelf null-modem cables canno

5421 Specifications...5320 PCI Resource Map...5019 DTE Inte

19 DTE Interface SignalsCIRCUIT AB - SIGNAL GROUND CONNECTOR NOTATION: DGND DIRECTION: Not applicableThis conductor directly connects the DTE circui

CIRCUIT CC - DCE READY (DATA SET READY) CONNECTOR NOTATION: DSR DIRECTION: From DCEThis signal indicates the status of the local DCE by reporting to

CIRCUIT DB - TRANSMIT SIGNAL ELEMENT TIMING (DCE SOURCE) CONNECTOR NOTATION:TXCLK (DCE) DIRECTION: From DCEThis signal, generated by the DCE, provid

20 PCI Resource MapListed below are the PCI resources used by the MPAC-100. Such informationmay be of use to customers writing their own device drive

21 SpecificationsBus interface: PCI, 32-bit bus, 5 volt onlyAMCC 5920 PCI ControllerPhysical Dimensions: approx. 4.5” x 2.5”Controller: Zilog Z

MPAC-100 User's ManualRevision 1.01June 2001P/N 940-0090-220

1 Introduction The Quatech MPAC-100 is a PCI Type card and is PCI PC Card StandardSpecification compliant. It provides a single-channel RS-232 synchro

2 Hardware InstallationHardware installation for the MPAC-100 is a very simple process:1. Turn off the power of the computer system in which the MPAC-

3 Windows 95/98 InstallationWindows 95/98 maintains a registry of all known hardware installed in yourcomputer. Inside this hardware registry Windows